Talk synopsis:
High-level synthesis (HLS) is the automated synthesis of a hardware circuit from a software program First proposed in the 1980s, and spending decades on the sidelines of mainstream RTL digital design, there has been tremendous buzz around HLS technology in recent years. HLS is on the upswing as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers having limited hardware expertise. The hope is that down the road, software developers can use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. In this talk, I will overview the trends behind the recent drive towards FPGA HLS and why the need for, and use of, HLS will only become more pronounced in the coming years. The talk will highlight current HLS research directions and expose some of the challenges for HLS that may hinder its update in the digital design community. I will describe work underway in the LegUp HLS project at the University of Toronto -- a publicly available HLS research tool that has been downloaded by over 5000 groups from around the world. LegUp HLS technology is being commercialized in a start-up company, LegUp Computing Inc. (https://www.legupcomputing.com/), which was founded in 2015 and received seed funding from Intel Capital in 2018. A key value proposition of LegUp HLS is FPGA-vendor agnosticism — synthesized circuits can be targeted to any FPGA.
Speaker biography:
Jason Anderson (http://janders.eecg.toronto.edu/) is Professor and Associate Chair, Research, with the Dept. of Electrical and Computer Engineering, University of Toronto, and holds the Jeffrey Skoll Endowed Chair. He joined the FPGA Implementation Tools Group, Xilinx, Inc., San Jose, CA, USA, in 1997, where he was involved in placement, routing, and synthesis. He became a Principal Engineer at Xilinx in 2007 and joined the university in 2008. His research interests are all aspects of tools, architectures, and circuits for FPGAs. He has co-authored over 90 peer-reviewed research publications, 4 book chapters, holds 29 U.S. patents, and was Program Co-Chair for FPL 2016, Program Chair for ACM FPGA 2017, and is General Chair for ACM FPGA 2018. He is Co-Founder and Chief Scientific Advisor of LegUp Computing Inc.
Panellist biography:
Andrea Borga is a telecoms engineer (Politecnico di Torino, Italy).
Being an open source enthusiast, and a patient promoter of its spread in
scientific communities, he co-founded Oliscience BV (Open Logic
Interconnects science). He is presently also part-time staff at Nikhef
(Amsterdam, The Netherlands), where he focuses on the engineering of
FPGA-based systems for large scientific experiments.
Panellist biography:
Uli has been working on free software for close to 30 years. During that
time he lead several projects like the GNU C library and contributed to
many others that make up a Linux system. These days he is investigating
mostly lowlevel technologies at the CPU-, OS-, and compiler-level for
HPC, specifically ML.
Panellist biography:
Hipolito Guzman-Miranda is an Associate Professor at the Department of Electronic Engineering, Universidad de Sevilla, Spain. His expertise is related to digital design, radiation effects on digital circuits, and design and development of fault injection platforms. Hipólito has authored more than 50 scientific publications and has participated and coordinated multiple research and technology transfer projects with the aerospace sector. He is the current Vice-Chair of the IEEE Industrial Electronics Society Technical Committee on Electronics System on Chip, and Associate Editor & Chief Publisher of IEEE Industrial Electronics Technology Transfer News. He is a free and open source enthusiast and is always looking for ways that the academic community can contribute towards open source design automation.
Talk synopsis:
In many ways, HDL developers have been many years behind their counterparts in the software world. One such area is core management. Where the software developers simply specify which libraries they depend on, HDL developers rely on copying around source code. Where software developers can select their build tool with a flick of a switch, HDL developers use tool-specific project files powered by custom makefiles.
FuseSoC rectifies this by bringing a modern package manager and a uniform build system to HDL developers, making it easy to reuse existing code, change tools and move projects between FPGAs from different vendors. Having been around for seven years there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools supported.
This presentation will give an overview of where FuseSoC can help spending less time on the cores, and more time on the core business
Speaker biography:
Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, the IP-XACT Python library. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.
Talk synopsis:
The “internet of everything” envisions trillions of connected objects loaded with high-
bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and
classification. While silicon access cost is naturally decreasing due to the twilight of the Moore’s law,
the access to hardware IPs still represents a huge barrier for innovative start-ups and companies
approaching the market of IoT. In this context, the recent growth of high-quality open source hardware
IPs represents a promising way to surpass this barrier, paving the way for a number of exciting
applications of open-source electronics. In this talk, I will describe the evolution of the open-source
Parallel-Ultra-Low-Power (PULP) platform as well as opportunities and challenges for next generation
open source computing systems.
Speaker biography:
Davide Rossi, received the PhD from the University of Bologna, Italy, in 2012. He has been a post
doc researcher in the Department of Electrical, Electronic and Information Engineering “Guglielmo
Marconi” at the University of Bologna since 2015, where he currently holds an assistant professor
position. His research interests focus on energy efficient digital architectures in the domain of
heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures,
design implementation strategies, and runtime support to address performance, energy efficiency, and
reliability issues of both high end embedded platforms and ultra-low-power computing platforms
targeting the IoT domain. In these fields, he has published more than 80 paper in international peer-
reviewed conferences and journals.
Talk synopsis:
ASTRONs mission is to make discoveries in radio astronomy happen. The high performance streaming data systems we build to do that naturally have FPGAs at their hearts. To balance project requirements, cost and availability of FPGA devices, ASTRON uses an approach that is both vendor and application independent. With generic, universal FPGA platforms (UniBoard, UniBoard2, Perentie), new science applications can take advantage of already available hardware. By also having a vendor independent VHDL library and tool flow, new FPGA hardware can also be adopted/developed with minimal firmware rework needed.
This talk is about the advantages of vendor independence and how we chose to implement this, covering VHDL source code, vendor IP, library structures and simulation and synthesis tools. Another important aspect is the automated regression testing of the firmware library as it is updated on a daily basis. All this is made possible and structured by ASTRONs scripted tool flow, which is to be released as open source on OpenCores.org. Finally, this talk will cover how and why ASTRON is going to release its firmware library on OpenCores, and the technical challanges in doing so.
Speaker biography:
Daniel van der Schuur is a digital designer at the Netherlands Institute for Radio Astronomy (ASTRON). As ASTRON designs, builds and operates complex high performance hybrid (FPGA, GPU, CPU, fiber networks) systems to make new discoveries, Daniel is passionate about reducing the time to science - from streaming system design to VHDL implementation.
Talk synopsis:
On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with only minor adjustments and no extra cost.
For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. UVVM (the open source Universal VHDL Verification Methodology) was developed to solve this and will reduce the verification time significantly while at the same time improving the product quality.
UVVM provides a very simple and powerful architecture that allow designers to build their own test harness much faster than ever before – using a mix of their own and open source verification components. UVVM also provides an architecture, methodology and library to allow VHDL verification components to be made extremely efficiently. And maybe the most important feature - UVVM allows the best possible testbench and test case overview using high level commands for both DUT interface control and synchronization.
The great overview, maintainability, extensibility, modifiability and reuse has resulted in an extraordinary fast spread of this methodology - and according to the 2018 Wilson Research report UVVM was the by far fastest growing FPGA verification methodology over the last two years.
UVVM is the new standardised VHDL testbench architecture, recommended by Doulos and backed by ESA (the European Space Agency) through a contract for further extension of the UVVM functionality.
This presentation will show you how simple this is to understand, build and control. It will also show the latest features from the ESA project and further planned extensions.
Speaker biography:
Espen Tallaksen is the managing director and founder of Bitvis, an independent design centre for embedded software and FPGA. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway, including his earlier founded company Digitas.
During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by a huge number of companies world-wide. He has given many presentations and keynotes on various technical aspects of FPGA development.
Panellist biography:
Clifford Wolf develops open source software, has been teaching at Metalab and collaborates and publishes with the Institute of Computer Technology, of the Vienna University of Technology. Clifford is best known for his Open Source EDA projects, including Yosys, SymbiYosys, nextpnr, Project IceStorm, and Project X-Ray. He is co-founder of Symbiotic EDA, a company focusing on formal hardware verification and advancing Open Source EDA tools. He is also an active contributor to RISC-V, author of riscv-formal, vice-chair of the RISC-V bit-manipulation work group, and member of the RISC-V formal specification work group.