|1030||LiteX: an open-source SoC builder and library based on Migen Python DSL
Florent Kermarrec, Sébastien Bourdeauducq, Jean-Christophe Le Lann and Hannah Badier (Enjoy-Digital, FR)
Speaker: Florent Kermarecc
Biography: Florent Kermarrec is a digital design engineer and founder of Enjoy-Digital which provides FPGA design services but also open-source tools/cores.
Abstract: LiteX  is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.
Full Paper Slides
|1050||On Hardware Verification In An Open Source Context
Ben Marshall (University of Bristol, UK)
Abstract: The last few decades have seen the complexity of commercial hardware designs increase by multiple orders of magnitude. This has driven corresponding increases in commercial tool capability and the development of industry standard methods to drive them. Over the same time period, open source hardware development has lagged severely behind in terms of the scale of attempted designs, as well as the tooling and methodology capability to realise them. This capability gap is particularly acute for verification flows. In this paper, we try to explain how this capability gap appeared, and what it means for a nascent open source EDA community. We also survey the state of the art in commercial verification techniques, and list alternative open source tools where available. Where open source alternatives are lacking, we make suggestions for closing the gap. We also discuss several human factors and challenges relevant to verification in an open source context, and suggest a change in mindset is needed to make open source hardware designs more trustworthy.
Full Paper Slides Slides+Notes
|1110||PyGears: A Functional Approach to Hardware Design
Bogdan Vukobratović, Andrea Erdeljan and Damjan Rakanović (University of Novi Sad, RS)
Speaker: Bogdan Vukobratović
Biography: Bogdan Vukobratovic holds a PhD in Electrical Engineering from the University of Novi Sad, Serbia. He has been working in the field of hardware acceleration for more than 8 years, both as a researcher and hardware designer.
Abstract: In this paper we propose a new hardware design methodology called Gears, and we introduce PyGears, a Python framework that facilitates designing hardware using the Gears methodology. Gears builds on top of the RTL methodology and focuses on hardware module composability, hence improving design reuse, scalability and testability. Gears methodology proposes building complex digital systems from small functional units that communicate exclusively via simple handshake interface called Data Transfer Interface (DTI). Such units form a category (from the mathematical field of Category Theory), and Gears then provides practical means for composing such units to implement a complex functionality using concepts from the Category Theory (like algebraic types and functors). On the other hand, PyGears helps describe these abstract composition operations in a way that is easy to read and debug, it compiles the design described in Python to SystemVerilog and allows simulating the design.
Full Paper Slides
|1400||Enabling FPGA Domain-specific Compilers Through Open Source
Alireza Kaviani and Chris Lavin (Xilinx Research Labs, USA)
Speaker: Alireza Kaviani
Biography: Alireza Kaviani is a distinguished Engineer at Xilinx Research Labs with an interest on the next generation FPGA architectures and tools. He has more than 20 years of FPGA and ASIC industry experience in the areas of architecture, tools, IC design, and applications. Alireza has authored more than 50 patents and publications in a number of areas, including clocking, asynchronous design, FPGA architecture and CAD tools. He holds a PhD degree from University of Toronto in Electrical and Computer Engineering.
Extended Abstract Slides
|1405||Minitracer: A minimalist requirements tracer for HDL designs
Carlos López-Melendo and Hipólito Guzmán-Miranda (University of Seville, ES)
Speaker: Hipólito Guzmán-Miranda
Biography: Hipolito Guzman-Miranda is an Associate Professor at the Department of Electronic Engineering, Universidad de Sevilla, Spain. His expertise is related to digital design, radiation effects on digital circuits, and design and development of fault injection platforms. Hipólito has authored more than 50 scientific publications and has participated and coordinated multiple research and technology transfer projects with the aerospace sector. He is the current Vice-Chair of the IEEE Industrial Electronics Society Technical Committee on Electronics System on Chip, and Associate Editor & Chief Publisher of IEEE Industrial Electronics Technology Transfer News. He is a free and open source enthusiast and is always looking for ways that the academic community can contribute towards open source design automation.
|1410||OpenFPGA: a Complete Open Source Framework for FPGA Prototyping
Baudouin Chauviere, Aurélien Alacchi, Edouard Giacomin, Xifan Tang and Pierre-Emmanuel Gaillardon (University of Utah, USA)
Speaker: Baudouin Chauviere
Biography: Baudouin Chauviere received his Electrical Engineer Master degree from CPE Lyon, France, in 2018. He is currently doing his Ph.D. thesis at the University of Utah, Salt Lake City, UT, USA, working on an open source tool allowing the prototyping of FPGAs. His other area of focus is resistive memory in the aim of building ReRAM-based FPGA designs.
Abstract: In this paper, we present OpenFPGA, an opensource FPGA IP generator allowing fast prototyping of customizable FPGA fabrics described using a high-level XML architecture description language. OpenFPGA consists of three tools: FPGA-Verilog, FPGA-SPICE and FPGA-Bistream. FPGAVerilog creates the Verilog netlist of the full FPGA fabric allowing a semi-custom design flow to automatize the layout generation. FPGA-SPICE generates SPICE netlists enabling accurate power and delay analysis using electrical simulations. FPGA-Bitstream provides programming support for the prototyped FPGAs and also enables functional verification during pre-silicon development.
Extended Abstract Slides Poster
|1415||Draft of CERN OHL (Open Hardware Licence) v2: We need your feedback
Tristan Gingold (CERN, CH)
|1420||GHDL: Present and Future
Tristan Gingold (CERN, CH)
|1500||"UVVM - The fastest growing FPGA verification methodology world-wide!"
Espen Tallaksen (Bitvis, NO)
Invited Paper Slides
|1545||PRGA: An Open-source Framework for Building and Using Custom FPGAs
Ang Li and David Wentzlaff (Princeton University, USA)
Speaker: Ang Li
Biography: Ang Li is a third-year PhD Candidate in the Princeton Parallel Research Group led by Prof. David Wentzlaff. His research interests include spatial, reconfigurable architectures, and the integration of these architectures into heterogeneous, general-purpose architectures.
Abstract: In this era where Moore’s Law is approaching its finale, industry has started looking for alternatives to conventional CPUs in order to meet the exploding needs of more diverse, complex and evolving applications. FPGAs are one of the most promising alternatives, offering performance, programmability, and flexibility. However, FPGAs are primarily available as packaged chips from a small number of manufacturers. The tool chains of these FPGAs remain closed-source, and the internal architectures remain a mystery to the public. As a consequence, academia and the open-source community face great difficulties trying to get involved in the development of FPGAs and their tools. In this paper, we present Princeton Reconfigurable Gate Array (PRGA), a highly customizable, scalable, and complete open-source framework for building and using custom FPGAs. The front-end of PRGA, the PRGA Builder, generates synthesizable RTL for a user-defined FPGA that can be fed to the ASIC design flow to enable taping out stand-alone or embedded FPGAs. PRGA Builder features high customizability, supporting heterogeneous logic blocks, custom IP cores, custom routing networks, etc.; it also features high scalability, scaling up to billions of basic elements. PRGA Builder also generates a set of files for the back-end of PRGA, the PRGA Tool Chain, which can synthesize, place & route, and generate the bitstream for a target RTL design using several open-source CAD tools. The bitstream can then be used to program the generated FPGA so as to implement the target design. We have tested PRGA with a few small-scale FPGA architectures and target designs. Preliminary results show that the runtime of the PRGA Builder scales linearly with the total number of logic elements and wiring resources, and the memory usage grows very slowly as the FPGA becomes larger.
Full Paper Slides
|1605||An Open-source Framework for Xilinx FPGA Reliability Evaluation
Aitzan Sari, Vasileios Vlagkoulis and Mihalis Psarakis (University of Piraeus, GR)
Speaker: Mihalis Psarakis
Biography: Mihalis Psarakis has a diploma in computer engineering from the University of Patras, Greece and a PhD degree in computer science from the University of Athens, Greece. He is an assistant Professor in the Department of Informatics, University of Piraeus, Greece. His research interests include functional testing of microprocessors and System-on-Chips, design of reliable embedded systems and reconfigurable computing. Abstract: The paper presents an open-source framework that provides access to the FPGA configuration memory and circuit logic via the JTAG protocol. By implementing various configuration memory functions, such as bitstream readback and verify, configuration frame write and read, configuration frame ECC monitoring, our tool can be used to support the design and evaluation of FPGA reliability methodologies. It mainly consists of: i) an on-chip logic to provide access to the configuration memory, embedded ECC core and DUT logic, ii) a software library of low-level JTAG functions and iii) a set of high-level configuration functions (GUI) to enable the development of target applications. The main benefits of the proposed framework, except its open-source architecture, are its low cost (no extra hardware), non-intrusiveness (no DUT modifications) and expandability (it can be easily extended to support new FPGA families). We demonstrate the applicability of the proposed framework with three use cases: radiation testing logger, configuration memory scrubber and fault injection platform.
Full Paper Slides
|1625||Python Wraps Yosys for Rapid Open-Source EDA Application Development
Benedikt Tutzer, Christian Krieg, Clifford Wolf and Axel Jantsch (TU Wien, AT)
Speaker: Benedikt Tutzer
Abstract: Yosys is an open-source synthesis and verification tool which natively supports Verilog-2005 and offers a variety of passes to allow a user to adapt the design and verification flow. A user can extend the functionality of Yosys with a plugin interface in C++. C++ is a powerful language, and it is easy to lose track in fixing low-level issues like memory allocation, instead of focusing on the original problem. This can significantly increase the length of the compile/debug cycle. Python, on the other hand, is a dynamically-typed, garbage-collected language which takes away low-level management from the user, who can focus on the original problem, and therefore keep the debug cycle short. Python is simple and easy to learn. We therefore propose pyosys, a script that generates Boost.Python wrappers around the C++ implementation of Yosys. These wrappers maintain seamless interoperability between C++ and Python. pyosys makes Python’s success accessible to Yosys: rapid application development. With pyosys, a user can interactively use Yosys in a Python session, with direct access to the Yosys data structures (e.g., design, modules, cells, wires) and methods (e.g., run pass, load plugin, get selection). In addition, the user can develop passes stepby-step directly in Python, with immediate feedback and debug capabilities. This is significant for scientists who can now test their algorithms using an easy-to-use and maintainable highlevel language. The results of their experiments are stored in Python objects, and can be directly processed with data analysis frameworks like scipy, machine learning libraries such as TensorFlow, and data visualization frameworks like matplotlib.
Full Paper Slides
|1645||"FuseSoC - Cores never been so much fun"
Olof Kindgren (Qamcom Research & Technology/FOSSi Foundation, SE)
Invited Paper Slides